The present invention relates to nonvolatile memories.
FIG. 1 illustrates a nonvolatile memory cell with a floating gate 110 located in a trench 114 formed in a semiconductor substrate. The cell is obtained by adapting a trench capacitor DRAM (dynamic random access random memory) fabrication process. See U.S. Pat. No. 5,932,908 issued Aug. 3, 1999 to Noble, entitled “TRENCH EPROM”, incorporated herein by reference. Trench 114 extends through a well 118 doped P− and a well 122 doped N+, to a region 126 doped P−. Dielectric 128 lines the trench. The capacitance of floating gate 110 is dominated by the capacitance between the floating gate and the N well 122.
Floating gate 110 serves as the gate of a vertical FET (field effect transistor). The channel of this transistor is located in P well 118. The source/drain regions are provided by N well 122 and an N+ diffusion region 130 located at the top of the trench.
Wordline 140 provides the gate for a lateral FET which serves as the select transistor of the memory cell. The channel of the select transistor is a region of P well 118. The source/drain regions are the region 130 and another N+ region 150 (bit line region).
The cell can be written by storing either a positive or a negative charge on the floating gate. The negative charge is stored by the channel hot electron injection. In this operation, bit line region 150 is grounded. Wordline 140 is brought up to some voltage VDD, turning on the select transistor. N well 122 is at 6V. Due to the capacitive coupling between the N well 122 and the floating gate, the floating gate voltage is raised, turning on the vertical FET. Hot electrons generated in the channel of the vertical FET are injected into the floating gate.
The negative charge is erased by Fowler-Nordheim tunneling from the floating gate to N+ region 130. In this operation, N well 122 is grounded, bit line region 150 is at 6V, and wordline 140 is at 8V.
Storing a positive charge on the floating gate is accomplished via Fowler-Nordheim tunneling of electrons to N+ region 130 (like the erase operation described above). The positive charge is erased by Fowler-Nordheim tunneling from P− region 126 to the floating gate.
To read the cell, a voltage difference of VDD is created between N well 122 and bit line region 150. Wordline 140 is at VDD. The current through the bit line region indicates the state of the memory cell.
One advantage of forming the floating gate in the trench is a small cell area. Another advantage is a high capacitive coupling between the floating gate and the N well 122 relative to the total floating gate capacitance. This high capacitive coupling efficiency (high capacitive coupling relative to the total floating gate capacitance) is easier to achieve than an efficient coupling between the floating and control gates in some non-trench structures, as described in the U.S. Pat. No. 5,932,908.
Another advantage is a close relationship to trench capacitor DRAM fabrication processes. This relationship facilitates integration of the floating gate memory and trench capacitor DRAM on one chip.